SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the IntelCore microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;[1] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation.[2] SSE4 extended the SSE3 instruction set which was released in early 2004. All software using previous Intel SIMD instructions (ex. SSE3) are compatible with modern microprocessors supporting SSE4 instructions. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.[3]
Like other previous generation CPU SIMD instruction sets, SSE4 supports up to 16 registers, each 128-bits wide which can load four 32-bit integers, four 32-bit single precision floating point numbers, or two 64-bit double precision floating point numbers.[1] SIMD operations, such as vector element-wise addition/multiplication and vector scalar addition/multiplication, process multiple bytes of data in a single CPU instruction. The parallel operation packs noticeable increases in performance. SSE4.2 introduced new SIMD string operations, including an instruction to compare two string fragments of up to 16 bytes each.[1] SSE4.2 is a subset of SSE4 and it was released a few years after the initial release of SSE4.
SSE4 subsets
Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the seven remaining instructions, is first available in Nehalem-based Core i7. Intel credits feedback from developers as playing an important role in the development of the instruction set.
Starting with Barcelona-based processors, AMD introduced the SSE4a instruction set, which has four SSE4 instructions and four new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the Bulldozer-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory.[4] Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until AVX.[5]
Name confusion
What is now known as SSSE3 (Supplemental Streaming SIMD Extensions 3), introduced in the Intel Core 2 processor line, was referred to as SSE4 by some media until Intel came up with the SSSE3 moniker. Internally dubbed Merom New Instructions, Intel originally did not plan to assign a special name to them, which was criticized by some journalists.[6] Intel eventually cleared up the confusion and reserved the SSE4 name for their next instruction set extension.[7]
Intel is using the marketing term HD Boost to refer to SSE4.[8]
New instructions
Unlike all previous iterations of SSE, SSE4 contains instructions that execute operations which are not specific to multimedia applications. It features a number of instructions whose action is determined by a constant field and a set of instructions that take XMM0 as an implicit third operand.
Several of these instructions are enabled by the single-cycle shuffle engine in Penryn. (Shuffle operations reorder bytes within a register.)
Compute eight offset sums of absolute differences, four at a time (i.e., |x0−y0|+|x1−y1|+|x2−y2|+|x3−y3|, |x0−y1|+|x1−y2|+|x2−y3|+|x3−y4|, ..., |x0−y7|+|x1−y8|+|x2−y9|+|x3−y10|); this operation is important for some HDcodecs, and allows an 8×8 block difference to be computed in fewer than seven cycles.[9] One bit of a three-bit immediate operand indicates whether y0 .. y10 or y4 .. y14 should be used from the destination operand, the other two whether x0..x3, x4..x7, x8..x11 or x12..x15 should be used from the source.
PHMINPOSUW
Sets the bottom unsigned 16-bit word of the destination to the smallest unsigned 16-bit word in the source, and the next-from-bottom to the index of that word in the source.
PMULDQ
Packed 32-bit signed "long" multiplication, two (1st and 3rd) out of four packed integers multiplied giving two packed 64-bit results.
PMULLD
Packed 32-bit signed "low" multiplication, four packed sets of integers multiplied giving four packed 32-bit results.
DPPS, DPPD
Dot product for AOS (Array of Structs) data. This takes an immediate operand consisting of four (or two for DPPD) bits to select which of the entries in the input to multiply and accumulate, and another four (or two for DPPD) to select whether to put 0 or the dot-product in the appropriate field of the output.
Conditional copying of elements in one location with another, based (for non-V form) on the bits in an immediate operand, and (for V form) on the bits in register XMM0.
The INSERTPS and PINSR instructions read 8, 16 or 32 bits from an x86 register or memory location and inserts it into a field in the destination register given by an immediate operand. EXTRACTPS and PEXTR read a field from the source register and insert it into an x86 register or memory location. For example, PEXTRD eax, [xmm0], 1; EXTRACTPS [addr+4*eax], xmm1, 1 stores the first field of xmm1 in the address given by the first field of xmm0.
This is similar to the TEST instruction, in that it sets the Z flag to the result of an AND between its operands: ZF is set, if DEST AND SRC is equal to 0. Additionally it sets the C flag if (NOT DEST) AND SRC equals zero.
This is equivalent to setting the Z flag if none of the bits masked by SRC are set, and the C flag if all of the bits masked by SRC are set.
PCMPEQQ
Quadword (64 bits) compare for equality
PACKUSDW
Convert signed DWORDs into unsigned WORDs with saturation.
MOVNTDQA
Efficient read from write-combining memory area into SSE register; this is useful for retrieving results from peripherals attached to the memory bus.
SSE4.2
SSE4.2 added STTNI (String and Text New Instructions),[10] several new instructions that perform character searches and comparison on two operands of 16 bytes at a time. These were designed (among other things) to speed up the parsing of XML documents.[11] It also added a CRC32 instruction to compute cyclic redundancy checks as used in certain data transfer protocols. These instructions were first implemented in the Nehalem-based Intel Core i7 product line, and complete the SSE4 instruction set. AMD on the other hand first added support starting with the Bulldozer microarchitecture. Support is indicated via the CPUID.01H:ECX.SSE42[Bit 20] flag.
Windows 11 24H2 requires the CPU to support SSE4.2, otherwise the Windows kernel is unbootable.[12] (Various unofficial Windows 11 variants, such as Tiny11 and Parallels virtualizations installations, bypass this requirement.)
Instruction
Description
CRC32
Accumulate CRC32C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41).[13][14]
PCMPESTRI
Packed Compare Explicit Length Strings, Return Index
Compare Packed Signed 64-bit data For Greater Than
POPCNT and LZCNT
These instructions operate on integer rather than SSE registers, because they are not SIMD instructions, but appear at the same time and although introduced by AMD with the SSE4a instruction set, they are counted as separate extensions with their own dedicated CPUID bits to indicate support. Intel implements POPCNT beginning with the Nehalem microarchitecture and LZCNT beginning with the Haswell microarchitecture. AMD implements both, beginning with the Barcelona microarchitecture.
The encoding of LZCNT takes the same encoding path as the encoding of the BSR (bit scan reverse) instruction. This results in an issue where LZCNT called on some CPUs not supporting it, such as Intel CPUs prior to Haswell, may incorrectly execute the BSR operation instead of raising an invalid instruction exception. This is an issue as the result values of LZCNT and BSR are different.
Trailing zeros can be counted using the BSF (bit scan forward) or TZCNT instructions.
Windows 11 24H2 requires the CPU to support POPCNT, otherwise the Windows kernel is unbootable.[15]
Instruction
Description
POPCNT
Population count (count number of bits set to 1). Support is indicated via the CPUID.01H:ECX.POPCNT[Bit 23] flag.[16]
LZCNT
Leading zero count. Support is indicated via the CPUID.80000001H:ECX.ABM[Bit 5] flag.[17]
SSE4a
The SSE4a instruction group was introduced in AMD's Barcelona microarchitecture. These instructions are not available in Intel processors. Support is indicated via the CPUID.80000001H:ECX.SSE4A[Bit 6] flag.[17]
