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AArch64 or ARM64 is the 64-bit Execution state of the ARM architecture family. It was first introduced with the Armv8-A architecture, and has had many extension updates.^[1]

• 64-bit:
  • Execution state: AArch64.
  • Instruction sets: A64.
• 32-bit:
  • Execution state: AArch32.
  • Instruction sets: A32 + T32.
  • Example: ARMv8-R, Cortex-A32.^[2]

• New instruction set, A64:
  • Has 31 general-purpose 64-bit registers.
  • Has dedicated zero or stack pointer (SP) register (depending on instruction).
  • The program counter (PC) is no longer directly accessible as a register.
  • Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
    • Has paired loads/stores (in place of LDM/STM).
    • No predication for most instructions (except branches).
  • Most instructions can take 32-bit or 64-bit arguments.
  • Addresses assumed to be 64-bit.
• Advanced SIMD (Neon) enhanced:
  • Has 32 × 128-bit registers (up from 16), also accessible via VFPv4.
  • Supports double-precision floating-point format.
  • Fully IEEE 754 compliant.
  • AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
• A new exception system:
  • Fewer banked registers and modes.
• Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.

Extension: Data gathering hint (ARMv8.0-DGH).

AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.

The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28.

Announced in October 2011,^[3] ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit Arm) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide user-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.^[4] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.^[5] Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A.^[6] The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.^[7]

ARMv8-A includes the VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.^[8]

An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.^[9] For example, the ARM Cortex-A32 supports only AArch32,^[10] the ARM Cortex-A34 supports only AArch64,^[11] and the ARM Cortex-A72 supports both AArch64 and AArch32.^[12] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.^[9]

In December 2014, ARMv8.1-A,^[13] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.

Instruction set enhancements included the following:

• A set of AArch64 atomic read-write instructions.
• Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
  • Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
  • Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
  • The instructions are added in vector and scalar forms.
• A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
• The optional CRC instructions in v8.0 become a requirement in ARMv8.1.

Enhancements for the exception model and memory translation system included the following:

• A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.
• An increased VMID range for virtualization; supports a larger number of virtual machines.
• Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
• The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
• A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
• Top byte ignore for memory tagging.^[14]

In January 2016, ARMv8.2-A was announced.^[15] Its enhancements fell into four categories:

• Optional half-precision floating-point data processing (half-precision was already supported, but not for processing, just as a storage format.)
• Memory model enhancements.
• Introduction of Reliability, Availability and Serviceability Extension (RAS Extension).
• Introduction of statistical profiling.

The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads.^[16][17] The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, the NEON extensions.

A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor; this computer^[18] was the fastest supercomputer in the world for two years, from June 2020^[19] to May 2022.^[20] A more flexible version, 2x256 SVE, was implemented by the AWS Graviton3 ARM processor.

SVE is supported by the GCC compiler, with GCC 8 supporting automatic vectorization^[17] and GCC 10 supporting C intrinsics. As of July 2020^[update], LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.^[21]

In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:^[22]

• Pointer authentication^[23] (AArch64 only); mandatory extension (based on a new block cipher, QARMA^[24]) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).
• Nested virtualization (AArch64 only).
• Advanced SIMD complex number support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.
• New FJCVTZS (Floating-point JavaScript Convert to Signed fixed-point, rounding toward Zero) instruction.^[25]
• A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of C++11/C11 (the default C++11/C11 consistency model was already supported in previous ARMv8).
• ID mechanism support for larger system-visible caches (AArch64 and AArch32).

ARMv8.3-A architecture is now supported by (at least) the GCC 7 compiler.^[26]

In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:^[27][28][29]

• "SHA3 / SHA512 / SM3 / SM4 crypto extensions." I.e. optional instructions.
• Improved virtualization support.
• Memory Partitioning and Monitoring (MPAM) capabilities.
• A new Secure EL2 state and Activity Monitors.
• Signed and unsigned integer dot product (SDOT and UDOT) instructions.

In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories:^[30][31][32]

• Memory Tagging Extension (MTE) (AArch64).^[33]
• Branch Target Indicators (BTI) (AArch64) to reduce "the ability of an attacker to execute arbitrary code". Like pointer authentication, the relevant instructions are no-ops on earlier versions of ARMv8-A.
• Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards".

On 2 August 2019, Google announced Android would adopt Memory Tagging Extension (MTE).^[34]

In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all the features from ARMv8.5.^[35][36][37] ARMv9-A also adds:

• Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grain Data Level Parallelism (DLP), to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use Neon.^[38] The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support SVE2.^[38][39]
• Transactional Memory Extension (TME). Following the x86 extensions, TME brings support for Hardware Transactional Memory (HTM) and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained Thread Level Parallelism (TLP), to allow more work done per thread.^[38] The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support TME.^[39]
• Confidential Compute Architecture (CCA).^[40][41]

In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories:^[30][42]

• General Matrix Multiply (GEMM).
• Bfloat16 format support.
• SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT.
• Enhancements for virtualization, system management and security.
• And the following extensions (that LLVM 11 already added support for^[43]):
  • Enhanced Counter Virtualization (ARMv8.6-ECV).
  • Fine-Grained Traps (ARMv8.6-FGT).
  • Activity Monitors virtualization (ARMv8.6-AMU).

For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.^[44]

In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories:^[30][45]

• Scalable Matrix Extension (SME)(ARMv9.2 only).^[46] SME adds new features to process matrices efficiently, such as:
  • Matrix tile storage.
  • On-the-fly matrix transposition.
  • Load/store/insert/extract tile vectors.
  • Matrix outer product of SVE vectors.
  • "Streaming mode" SVE.
• Enhanced support for PCIe hot plug (AArch64).
• Atomic 64-byte load and stores to accelerators (AArch64).
• Wait For Instruction (WFI) and Wait For Event (WFE) with timeout (AArch64).
• Branch-Record recording (ARMv9.2 only).
• Call Stack Recorder

In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories:^[30][47]

• Non-maskable interrupts (AArch64).
• Instructions to optimize memcpy() and memset() style operations (AArch64).
• Enhancements to PAC (AArch64).
• Hinted conditional branches (AArch64).

LLVM 15 supports ARMv8.8-A and ARMv9.3-A.^[48]

In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including:^[49]

• Virtual Memory System Architecture (VMSA) enhancements.
  • Permission indirection and overlays.
  • Translation hardening.
  • 128-bit translation tables (ARMv9 only).
• Scalable Matrix Extension 2 (SME2) (ARMv9 only).
  • Multi-vector instructions.
  • Multi-vector predicates.
  • 2b/4b weight compression.
  • 1b binary networks.
  • Range Prefetch.
• Guarded Control Stack (GCS) (ARMv9 only).
• Confidential Computing.
  • Memory Encryption Contexts.
  • Device Assignment.

In October 2023, ARMv9.5-A was announced, including:^[50]

• FP8 support (E5M2 and E4M3 formats) added to:
  • SME2
  • SVE2
  • Advanced SIMD (Neon)
• Live migration of Virtual Machines using Hardware Dirty state tracking structures (FEAT_HDBSS)
• Checked Point Arithmetic
• Support for using a combination of the PC and SP as the modifier when generating or checking Pointer Authentication codes.
• Support for Realm Management Extension (RME) enabled designs, support for non-secure only in the Granule Protection Tables and the ability to disable certain Physical Address Spaces (PAS).
• EL3 configuration write-traps.
• Breakpoint support for address range and mismatch triggering without the need for linking.
• Support for efficiently delegating SErrors from EL3 to EL2 or EL1.

In October 2024, ARMv9.6-A was announced, including:^[51]

• Improved SME efficiency with structured sparsity and quarter tile operations
• MPAM Domains to better support shared-memory computer systems on multi-chiplet and multi-chip systems
• Hypervisor memory control for Trace and Statistical Profiling on virtual machines
• Improved Caching and Data Placement
• Granular Data Isolation for Confidential Compute
• Bitwise locking of EL1 system registers
• Improved scaling of Granular Protection Tables (GPT) for large memory systems
• New SVE instructions for expand/compact and finding first/last active element
• Additional unprivileged load and store instructions to enable OS to interact with application memory
• New compare and branch instruction
• Injection of Undefined-Instruction exceptions from EL3

This section needs expansion with: examples and additional citations. You can help by adding to it. Relevant discussion may be found on Talk:AArch64. (May 2021)

The ARM-R architecture, specifically the Armv8-R profile, is designed to address the needs of real-time applications, where predictable and deterministic behavior is essential. This profile focuses on delivering high performance, reliability, and efficiency in embedded systems where real-time constraints are critical.

With the introduction of optional AArch64 support in the Armv8-R profile, the real-time capabilities have been further enhanced. The Cortex-R82^[52] is the first processor to implement this extended support, bringing several new features and improvements to the real-time domain.^[53]

1. AArch64 Instruction Set (A64):
   • The A64 instruction^[25] set in the Cortex-R82 provides 64-bit data handling and operations, which improves performance for certain computational tasks and enhances overall system efficiency.^[52]
   • Example Instruction: ADD X0, X1, X2 adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.
2. Enhanced Memory Management:
   • Memory Barrier Instructions: The Cortex-R82 introduces improved memory barrier instructions to ensure proper ordering of memory operations, which is critical in real-time systems where the timing of memory operations must be strictly controlled.^[54]
     • Data Synchronization Barrier (DSB): Ensures that all data accesses before the barrier are completed before continuing with subsequent operations.
     • Data Memory Barrier (DMB): Guarantees that all memory accesses before the barrier are completed before any memory accesses after the barrier can proceed.
   • Example: In a real-time automotive control system, DSB might be used to ensure that sensor data is fully written to memory before the system proceeds with processing or decision-making, preventing data corruption or inconsistencies.
3. Improved Address Space:
   • 64-bit Addressing: AArch64 allows the Cortex-R82 to address a much larger memory space compared to its 32-bit predecessors, making it suitable for applications requiring extensive memory.
   • Example: A complex industrial automation system can utilize the expanded address space to manage large data sets and buffers more efficiently, improving system performance and capability.
4. Real-Time Performance Enhancements:
   • Interrupt Handling: With AArch64 support, the Cortex-R82 can handle interrupts with lower latency and improved predictability, crucial for real-time operations.
   • Example: In a robotics application, the Cortex-R82's enhanced interrupt handling can ensure timely responses to external stimuli, such as changes in sensor data or control commands.

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