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__DTSUBSCRIBEBUTTONDESKTOP__{"headingLevel":2,"name":"h-Moxfyre-2007-07-23T18:14:00.000Z","type":"heading","level":0,"id":"h-PIC_is_not_RISC-2007-07-23T18:14:00.000Z","replies":["c-Moxfyre-2007-07-23T18:14:00.000Z-PIC_is_not_RISC"],"text":"PIC is not RISC","linkableTitle":"PIC is not RISC"}-->
__DTSUBSCRIBEBUTTONMOBILE__{"headingLevel":2,"name":"h-Moxfyre-2007-07-23T18:14:00.000Z","type":"heading","level":0,"id":"h-PIC_is_not_RISC-2007-07-23T18:14:00.000Z","replies":["c-Moxfyre-2007-07-23T18:14:00.000Z-PIC_is_not_RISC"],"text":"PIC is not RISC","linkableTitle":"PIC is not RISC"}-->
Including the PIC microcontrollers as a RISC architecture seems pretty questionable to me... the only RISC-like thing about them is their small instruction set. Otherwise, the PIC16 ISA is basically accumulator-based, rather than including a set of general purpose registers. There's no way to implement a stack efficiently, the instruction set is totally non-orthogonal, all kinds of bank switching shenanigans are needed to access memory. It's basically a mess. The newer PIC18 instruction set improves this somewhat, maybe to the extent that the 386 made the 8086 instruction set more orthogonal by not tying specific registers to specific addressing modes. But PIC is definitely not RISC, as can be seen by comparing it to the Atmel AVR microcontrollers which have nearly identical hardware but a sane and orthogonal instruction set. So I'm going to remove PIC from this template. MOXFYRE (contrib) 18:14, 23 July 2007 (UTC)[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2007-07-23T18:14:00.000Z","author":"Moxfyre","type":"comment","level":1,"id":"c-Moxfyre-2007-07-23T18:14:00.000Z-PIC_is_not_RISC","replies":[]}}-->
__DTSUBSCRIBEBUTTONDESKTOP__{"headingLevel":2,"name":"h-99Electrons-2019-03-13T01:34:00.000Z","type":"heading","level":0,"id":"h-Requested_move_13_March_2019-2019-03-13T01:34:00.000Z","replies":["c-StraussInTheHouse-2019-03-26T20:09:00.000Z-Requested_move_13_March_2019","c-99Electrons-2019-03-13T01:34:00.000Z-Requested_move_13_March_2019"],"text":"Requested move 13 March 2019","linkableTitle":"Requested move 13 March 2019"}-->
__DTSUBSCRIBEBUTTONMOBILE__{"headingLevel":2,"name":"h-99Electrons-2019-03-13T01:34:00.000Z","type":"heading","level":0,"id":"h-Requested_move_13_March_2019-2019-03-13T01:34:00.000Z","replies":["c-StraussInTheHouse-2019-03-26T20:09:00.000Z-Requested_move_13_March_2019","c-99Electrons-2019-03-13T01:34:00.000Z-Requested_move_13_March_2019"],"text":"Requested move 13 March 2019","linkableTitle":"Requested move 13 March 2019"}-->
The following is a closed discussion of a requested move. Please do not modify it. Subsequent comments should be made in a new section on the talk page. Editors desiring to contest the closing decision should consider a move review after discussing it on the closer's talk page. No further edits should be made to this section.
The result of the move request was: moved (closed by non-admin page mover) SITH(talk)20:09, 26 March 2019 (UTC)[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2019-03-26T20:09:00.000Z","author":"StraussInTheHouse","type":"comment","level":1,"id":"c-StraussInTheHouse-2019-03-26T20:09:00.000Z-Requested_move_13_March_2019","replies":[],"displayName":"SITH"}}-->
Template:RISC-based processor architectures → Template:RISC architectures – The current name is overly verbose ("RISC-based processor" is redundant, it's understood that RISC relates to the processor), unwieldy, and potentially ambiguous ("processor architecture" could be reasonably construed to mean microarchitecture.). The current name is also unpleasant and makes little sense if the RISC acronym is expanded: reduced instruction set computer-based processor architecture. "RISC architectures" succinctly conveys the template's purpose. 99Electrons (talk) 01:34, 13 March 2019 (UTC) --Relisting.KCVelaga (talk) 14:59, 21 March 2019 (UTC)[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2019-03-13T01:34:00.000Z","author":"99Electrons","type":"comment","level":1,"id":"c-99Electrons-2019-03-13T01:34:00.000Z-Requested_move_13_March_2019","replies":["c-Editor-1-2019-03-13T12:43:00.000Z-99Electrons-2019-03-13T01:34:00.000Z","c-Da\u00df_W\u00f6lf-2019-03-23T19:00:00.000Z-99Electrons-2019-03-13T01:34:00.000Z"]}}-->
SupportEditor-1 (talk) 12:43, 13 March 2019 (UTC)[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2019-03-13T12:43:00.000Z","author":"Editor-1","type":"comment","level":2,"id":"c-Editor-1-2019-03-13T12:43:00.000Z-99Electrons-2019-03-13T01:34:00.000Z","replies":[]}}-->
Support per nom. DaßWölf19:00, 23 March 2019 (UTC)[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2019-03-23T19:00:00.000Z","author":"Da\u00df W\u00f6lf","type":"comment","level":2,"id":"c-Da\u00df_W\u00f6lf-2019-03-23T19:00:00.000Z-99Electrons-2019-03-13T01:34:00.000Z","replies":[],"displayName":"Da\u00df"}}-->
The above discussion is preserved as an archive of a requested move. Please do not modify it. Subsequent comments should be made in a new section on this talk page or in a move review. No further edits should be made to this section.
__DTSUBSCRIBEBUTTONDESKTOP__{"headingLevel":2,"name":"h-93.172.61.203-2021-02-03T12:19:00.000Z","type":"heading","level":0,"id":"h-POWER_is_(still)_not_historic-2021-02-03T12:19:00.000Z","replies":["c-93.172.61.203-2021-02-03T12:19:00.000Z-POWER_is_(still)_not_historic"],"text":"POWER is (still) not historic","linkableTitle":"POWER is (still) not historic"}-->
__DTSUBSCRIBEBUTTONMOBILE__{"headingLevel":2,"name":"h-93.172.61.203-2021-02-03T12:19:00.000Z","type":"heading","level":0,"id":"h-POWER_is_(still)_not_historic-2021-02-03T12:19:00.000Z","replies":["c-93.172.61.203-2021-02-03T12:19:00.000Z-POWER_is_(still)_not_historic"],"text":"POWER is (still) not historic","linkableTitle":"POWER is (still) not historic"}-->
There are POWER servers around and IBM is still releasing POWER chipsets. I am going to move it to "active" 93.172.61.203 (talk) 12:19, 3 February 2021 (UTC) Nevermind, I see the POWER is historic, while Power ISA is current[reply]__DTELLIPSISBUTTON__{"threadItem":{"timestamp":"2021-02-03T12:19:00.000Z","author":"93.172.61.203","type":"comment","level":1,"id":"c-93.172.61.203-2021-02-03T12:19:00.000Z-POWER_is_(still)_not_historic","replies":[]}}-->