Low voltage complementary metal oxide semiconductor (LVCMOS) is a low voltage class of CMOS technology digital integrated circuits.
To obtain better performance and lower costs, semiconductor manufacturers reduce the device geometries of integrated circuits. With each reduction the associated operating voltage must also be reduced in order to maintain the same basic operational characteristics of the transistors. As semiconductor technology has progressed, LVCMOS power supply voltage and interface standards for decreasing voltages have been defined by the Joint Electron Device Engineering Council (JEDEC) for digital logic levels lower than 5 volts.
The original LVCMOS standard of 3.3 V was established in the early 1970s. The CMOS technology of that time could only reliably work at a voltage above 3 V and 3.3 V is already an available voltage regulator standard (seen on e.g. the Apollo Guidance Computer).[1] The JEDEC standard was established in 1994.[2]
