Block diagram of the Platform Controller Hub–based chipset architecture, including an Integrated Memory Controller (IMC) in the CPUAn Intel DH82H81 PCH with its die exposed
The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset since the release of the Zen architecture in 2017.[1] AMD no longer uses its equivalent for the PCH, the Fusion controller hub (FCH).
Overview
Intel Cannon Lake Platform Controller Hub die
The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Under the Hub Architecture, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.[2]
As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge and its functions are now eliminated completely: The memory controller, PCI Express lanes for expansion cards and other northbridge functions are now incorporated into the CPU die as a system agent (Intel) or packaged in the processor on an I/O die (AMD Zen 2).
The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions, replacing it. The system clock was previously a connection to a dedicated chip but is now incorporated into the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is used only when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets. AMD's chipsets instead use several PCIe lanes to connect with the CPU while also providing their own PCIe lanes, which are also provided by the processor itself.[3][4] The chipset also contains the Nonvolatile BIOS memory.
With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.
This style began in Nehalem and will remain for the foreseeable future, through Cannon Lake.
Phase-out
Beginning with ultra-low-power Haswells and continuing with mobile Skylake processors, Intel incorporated the southbridge IO controllers into the CPU package, eliminating the PCH for a system in package (SOP) design with two dies; the larger die being the CPU die, the smaller die being the PCH die.[5] Rather than DMI, these SOPs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.[needs update]
AMD's FCH has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.[6] However, since the release of the Zen architecture, there's still a component called a chipset which only handles relatively low speed I/O such as USB and SATA ports and connects to the CPU with a PCIe connection. In these systems all PCIe connections are routed directly to the CPU.[7] The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I/O.[8]
AMD server and laptop CPUs adopt a self contained system on chip (SoC) design instead which doesn't require a chipset.[9][10][11]
Bogus USB ports will be detected by desktop PCHs equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Applying AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
Bogus USB ports will be detected by mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Applying AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
Reading the HPET comparator timer immediately after a write returns the old value (erratum 14)
SATA 6 Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)
Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.
This section's factual accuracy may be compromised due to out-of-date information. Please help update this article to reflect recent events or newly available information.(December 2012)
In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. The bug was present in revision B2 of the chipsets, and was fixed with B3. Z68 did not have this bug, since the B2 revision for it was never released. 6 Gbit/s ports were not affected. This bug was especially a problem with the H61 chipset, which only had 3 Gbit/s SATA ports. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[14][15]
Nearly all produced motherboards using Cougar Point chipsets were designed to handle Sandy Bridge, and later Ivy Bridge, processors. ASRock produced one motherboard for LGA 1156 processors, based on P67 chipset, the P67 Transformer. It exclusively supports Lynnfield Core i5/i7 and Xeon processors, using LGA 1156 socket. After revision B2 of Cougar Point chipsets was recalled, ASRock decided not to update the P67 Transformer motherboard, and was discontinued. Some small Chinese manufacturers are producing LGA 1156 motherboards with H61 chipset.
Whitney Point
Whitney Point is the codename of a PCH in the Oak Trail tablet platform for AtomLincroft microprocessors.
Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets (except PCH HM75) have integrated USB 3.0.[16]
Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms.[19] Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.[20]
Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[21][22]
A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[28][29] This issue is corrected in C2 stepping level of the Lynx Point chipset.[30]
Wellsburg
Wellsburg is the codename for the C610-series PCH, supporting the Haswell-E (Core i7 Extreme), Haswell-EP (Xeon E5-16xx v3 and Xeon E5-26xx v3), and Broadwell-EP (Xeon E5-26xx v4) processors. Generally similar to Patsburg, Wellsburg consumes only up to 7 W when fully loaded.[31]
Wellsburg has the following variations:
DH82029 (PCH C612), intended for servers and workstations
EY82C621 (PCH C621), intended for servers and workstations
EY82C622 (PCH C622), intended for servers and workstations
EY82C624 (PCH C624), intended for servers and workstations
EY82C625 (PCH C625), intended for servers and workstations
EY82C626 (PCH C626), intended for servers and workstations
EY82C627 (PCH C627), intended for servers and workstations
EY82C628 (PCH C628), intended for servers and workstations
Basin Falls
Basin Falls is the codename for the C400-series PCH, supporting Skylake-X/Kaby Lake-X processors (branded Core i9 Extreme and "Skylake-W" Xeon). Generally similar to Wellsburg, Basin Falls consumes only up to 6 W when fully loaded.
Basin Falls has the following variations:
GL82C422 (PCH C422), intended for servers and workstations
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