Two separate address busses driving the 8-bit data bus: a 24-bit "Bus A" for general access, and an 8-bit "Bus B" mainly for APU and PPU registers
Performance
The CPU as a whole employs a variable-speed system bus, with bus access times determined by the memory location accessed. The bus runs at 3.58 MHz for non-access cycles and when accessing Bus B and most internal registers, and either 2.68 or 3.58 MHz when accessing Bus A. It runs at 1.79 MHz only when accessing the controller port serial-access registers.[1] It works at approximately 1.5 MIPS, and has a theoretical peak performance of 1.79 million 16-bit operations per second.