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System Management Mode (SMM, sometimes called ring −2 in reference to protection rings)^[1][2] is an operating mode of x86 central processor units (CPUs) in which all normal execution, including the operating system, is suspended. An alternate software system which usually resides in the computer's firmware, or a hardware-assisted debugger, is then executed with high privileges.

It was first released with the Intel 386SL.^[3][4] While initially special SL versions were required for SMM, Intel incorporated SMM in its mainline 486 and Pentium processors in 1993. AMD implemented Intel's SMM with the Am386 processors in 1991.^[5] It is available in all later microprocessors in the x86 architecture.^{[citation needed]}

In ARM architecture the Exception Level 3 (EL3) mode is also referred as Secure Monitor Mode or System Management Mode.^[6]

SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM designed code. It is intended for use only by system firmware (BIOS or UEFI), not by applications software or general-purpose systems software. The main benefit of SMM is that it offers a distinct and easily isolated processor environment that operates transparently to the operating system or executive and software applications.^{[citation needed]}

In order to achieve transparency, SMM imposes certain rules. The SMM can only be entered through SMI (System Management Interrupt). The processor executes the SMM code in a separate address space (SMRAM) that has to be made inaccessible to other operating modes of the CPU by the firmware.^[7]

System Management Mode can address up to 4 GB memory as huge real mode. In x86-64 processors, SMM can address >4 GB memory as real address mode.^[8]

Initially, System Management Mode was used for implementing power management and hardware control features like Advanced Power Management (APM). However, BIOS manufacturers and OEMs have relied on SMM for newer functionality like Advanced Configuration and Power Interface (ACPI).^[9][10]

Some uses of the System Management Mode are:

• Handle system events like memory or chipset errors
• Manage system safety functions, such as shutdown on high CPU temperature
• System Management BIOS (SMBIOS)
• Advanced Configuration and Power Interface
• Control power management operations, such as managing the voltage regulator module and LPCIO (super I/O or embedded controller)
• Emulate USB mouse/keyboard as PS/2 mouse/keyboard (often referred to as USB legacy support)^[11]
• Centralize system configuration, such as on Toshiba and IBM/Lenovo notebook computers
• Managing the Trusted Platform Module (TPM)^[12]
• BIOS-specific hardware control programs, including USB hotswap and Thunderbolt hotswap in operating system runtime^[13]

System Management Mode can also be abused to run high-privileged rootkits, as demonstrated at Black Hat 2008^[14] and 2015.^[15]

SMM is entered via the SMI (system management interrupt), which is invoked by:

• Motherboard hardware or chipset signaling via a designated pin SMI# of the processor chip.^[16] This signal can be an independent event.
• Software SMI triggered by the system software via an I/O access to a location considered special by the motherboard logic (port 0B2h is common).^[17]
• An I/O write to a location which the firmware has requested that the processor chip act on.

By entering SMM, the processor looks for the first instruction at the address SMBASE (SMBASE register content) + 8000h (by default 38000h), using registers CS = 3000h and EIP = 8000h. The CS register value (3000h) is due to the use of real-mode memory addresses by the processor when in SMM. In this case, the CS is internally appended with 0h on its rightmost end.

By design, the operating system cannot override or disable the SMI. Due to this fact, it is a target for malicious rootkits to reside in,^[18][19] including NSA's "implants",^[20] which have individual code names for specific hardware, like SOUFFLETROUGH for Juniper Networks firewalls,^[21] SCHOOLMONTANA for J-series routers of the same company,^[22] DEITYBOUNCE for DELL,^[23] or IRONCHEF for HP Proliant servers.^[24]

Improperly designed and insufficiently tested SMM BIOS code can make the wrong assumptions and not work properly when interrupting some other x86 operating modes like PAE or 64-bit long mode.^[25] According to the documentation of the Linux kernel, around 2004, such buggy implementations of the USB legacy support feature were a common cause of crashes, for example, on motherboards based on the Intel E7505 chipset.^[11]

Since the SMM code (SMI handler) is installed by the system firmware (BIOS), the OS and the SMM code may have expectations about hardware settings that are incompatible, such as different ideas of how the Advanced Programmable Interrupt Controller (APIC) should be set up.

Operations in SMM take CPU time away from the applications, operating-system kernel and hypervisor, with the effects magnified for multicore processors, since each SMI causes all cores to switch modes.^[26] There is also some overhead involved with switching in and out of SMM, since the CPU state must be stored to memory (SMRAM) and any write-back caches must be flushed. This can destroy real-time behavior and cause clock ticks to get lost. The Windows and Linux kernels define an "SMI Timeout" setting – a period within which SMM handlers must return control to the operating system, or it will "hang" or "crash".

The SMM may disrupt the behavior of real-time applications with constrained timing requirements.

A logic analyzer may be required to determine whether the CPU has entered SMM (checking state of SMIACT# pin of CPU).^[16] Recovering the SMI handler code to analyze it for bugs, vulnerabilities and secrets requires a logic analyzer or disassembly of the system firmware.

• Coreboot – includes an open-source SMM/SMI handler implementation for some chipsets
• Intel 80486SL
• LOADALL
• MediaGX – a processor which emulates nonexistent hardware via SMM
• Ring −3
• Unified Extensible Firmware Interface (UEFI)
• Basic Input/Output System (BIOS)
• Speculative execution CPU vulnerabilities

• US patent 5175853, James Kardach; Gregory Mathews & Cau Nguyen et al., "Transparent system interrupt", published 1992-12-29, issued 1992-12-29, assigned to Intel Corporation 
• AMD Hammer BIOS and Kernel Developer's guide, Chapter 6 (archived from the original on 7 December 2008)
• Intel 64 and IA-32 Architectures Developer's Manual, Volume 3C, Chapter 34