This article needs to be updated. Please help update this article to reflect recent events or newly available information.(October 2023)
Around the time that the Pentium 4 processor was introduced, Intel's Xeon line diverged from its line of desktop processors, which at the time was using the Pentium branding.
The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.
The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub, on the other hand, connects to lower-speed I/O, such as SATA, PCI, USB, and Ethernet.
The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2 GB of main memory remained. These support Slot 2.
There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.
Eight processor P6-based Xeon chipset
In August 1999 Intel began shipping the Profusion PCIset.[1] The chipset was based on technology developed by the Corollary company, which Intel acquired.[2] It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them.[3][4][5] Profusion supported up to 32 GB of memory. It saw some limited competition from the NEC Aqua II chipset.[6] Another minor player in the eight-way space was Axil Computer's NX801,[2] which was used in an 8-way (two buses) Pentium Pro design, commercialized by Data General as their AV-8600 computer.[7]
E7500 corresponded to the first Northwood-based Pentium4 Xeons, E7501 is essentially identical but supports faster FSB and memory. The E7320, E7520 and E7525 chipsets correspond to Prescott-based Pentium4 Xeons, and differ mainly in their PCI Express support. These support Socket 604. The Intel 875P chipset was used in some two-socket motherboards for Xeons.[8][9][10][11]
Two channels of unbuffered ECC and non-ECC DDR DIMMs (registered ECC is not supported) at 133 MHz, 166 MHz or 200 MHz (DDR-266/333/400)
66 MHz CSA interface for Gigabit LAN. MCH is connected to ICH via 66 MHz 8-bit (266 MT/s) Hub Interface v1.5. A 6300ESB ICH provides up to four 32-bit and/or 64-bit PCI-X at 33 or 66 MHz. Intel E7210 is server variant of 875P (Socket 478) without AGP, it can be used in dual Socket 604 configurations.[14]
Two channels of registered DDR-333 or DDR2-400 SDRAM
One ×8 PCI Express interface with max. theoretical bandwidth of 4GB/s, which may be configured as two ×4 PCIe interfaces.[a] A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.
6300ESB, or 82801ER (ICH5R)
E7500
Plumas
400 MT/s
Two channels of ECC DDR SDRAM at 100 MHz (3.2 GB/s peak)
Three ECC 1 GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533 MB/s (66 MHz ×4) connector for ICH3-S
Two channels of ECC DDR SDRAM at 133 MHz (4.2 GB/s peak)
AGP 8× port, three ECC 1 GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533 MB/s (66 MHz ×4) connector for ICH4
Two channels of registered DDR-333 or DDR2-400 SDRAM
Three ×8 PCI Express interfaces each with max. theoretical bandwidth of 4GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.
One ×16 and one ×8 PCI Express interface. A 6700PXH can be attached.
Note that the 82870P2 chips of E7500, E7501 and E7505 were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.
As Intel didn't have a 4P-capable chipset for NetBurst-based Xeons until 2005, for three years ServerWorks GC-HE served as the de facto standard MP chipset, even being used in Intel's own motherboards (SPSH4 and SRSH4).[19]
3000 and 3010 are an update on the E7230 chipset, codenamed Mukilteo, which has specifications very similar to the 3000 chipset.[22] E7230 was preceded by E7221, which was Intel's first strictly single-socket server chipset.
These chipsets use a 'dual independent bus' design, in which each socket has its own connection to the chipset. These use the LGA 771 socket. The datasheets omit the 667 MT/s FSB support, so 5400 may support it too.
A snoop filter comprising about 1 MB of SRAM for coverage of 16 MB of cache.
Four channels of FB-DIMM at 533 or 667 MHz, up to 64 GB
Six PCIe ×4 ports, of which two are normally used for communication with IOCH and the other four are combined into a ×16 port, and a seventh ×4 port only for IOCH.
The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 (initial codename Tylersburg-EP) chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity