Digital timing diagram

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A digital timing diagram represents a set of signals in the time domain.^[1] A timing diagram can contain many rows, usually one of them being the clock. It is a tool commonly used in digital electronics, hardware debugging, and digital communications. Besides providing an overall description of the timing relationships, the digital timing diagram can help find and diagnose digital logic hazards.

Diagram convention

Most timing diagrams use the following conventions:

Higher value is a logic one
Lower value is a logic zero
A slot showing a high and low is an either-or (such as on a data line)
A Z indicates high impedance
A greyed out slot is a don't-care or indeterminate.

Example: SPI bus timing

The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus. Most SPI master nodes can set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL and the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1, then the data is delayed by one-half clock cycle.

SPI operates in the following way:

The master determines an appropriate CPOL & CPHA value
The master pulls down the slave select (SS) line for a specific slave chip
The master clocks SCK at a specific frequency
During each of the eight clock cycles, the transfer is full duplex:
- The master writes on the MOSI line and reads the MISO line
- The slave writes on the MISO line and reads the MOSI line
When finished the master can continue with another byte transfer or pull SS high to end the transfer

When a slave's SS line is high, both its MISO and MOSI line should be high impedance to avoid disrupting a transfer to a different slave. Before SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also, before the SS is pulled low, the "cycle #" row is meaningless and is shown greyed out.

Note that for CPHA=1, the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed out before that.

A more typical timing diagram has just a single clock and numerous data lines.

Software

The following diagram software may be used to draw timing diagrams:

PlantUML^[1]
Timing Diagrammer^[2]

References

^ ^a ^b "Timing Diagram". PlantUML. 2024. Archived from the original on 11 December 2024. Retrieved 10 February 2023.
^ "TimingDiagrammer". GitHub. Archived from the original on 21 January 2023. Retrieved 10 February 2023.

External links

Wikimedia Commons has media related to Digital timing diagrams.

Wavedrom is an online timing diagram editor.
Timing Diagrammer has a Windows binary.

v t e Digital electronics
Components	Transistor Resistor Inductor Capacitor Printed electronics Printed circuit board Electronic circuit Flip-flop Memory cell Combinational logic Sequential logic Logic gate Boolean circuit Integrated circuit (IC) Hybrid integrated circuit (HIC) Mixed-signal integrated circuit Three-dimensional integrated circuit (3D IC) Emitter-coupled logic (ECL) Erasable programmable logic device (EPLD) Macrocell array Programmable logic array (PLA) Programmable logic device (PLD) Programmable Array Logic (PAL) Generic Array Logic (GAL) Complex programmable logic device (CPLD) Field-programmable gate array (FPGA) Field-programmable object array (FPOA) Application-specific integrated circuit (ASIC) Tensor Processing Unit (TPU)
Theory	Digital signal Boolean algebra Logic synthesis Logic in computer science Computer architecture Digital signal Digital signal processing Circuit minimization Switching circuit theory Gate equivalent
Design	Logic synthesis Place and route Placement Routing Transaction-level modeling Register-transfer level Hardware description language High-level synthesis Formal equivalence checking Synchronous logic Asynchronous logic Finite-state machine Hierarchical state machine
Applications	Computer hardware Hardware acceleration Digital audio radio Digital photography Digital telephone Digital video cinematography television Electronic literature
Design issues	Metastability Runt pulse

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